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MIC Tutorial

 

This is a brief tutorial: PRELIMINARY RELEASE

 

Intel Phi Coprocessor (MIC - Many Integrated Core)

Intel Xeon Phi is the first Intel Many Integrated Core (Intel MIC) architecture product.  Each card consists of 60 physical cores (@1.1 Ghz) and each core is able to handle up to 4 thread using hyperthreading, achieving a theoretical peak of more of 1 Tflops in double precision.

Two different way of emploing the Phi coprocessore are avalible:

Offload mode: in this way part of the computation, the most computational intensive one, is dispatched to the Phi coprocessor from the CPU. This can be obtained using ad hoc directive to insert inside your code.

Native mode: all the simulation is perfomed directly on one or more Phi coprocessor, without using the host CPU (unless for cross-compiling). In this configuration a OpenMP, MPI o hybrid code can easily cross-compiled for Phi coprocessor: it can be seen as a single shared memory machine with 60 physical core, each of them able to handle up to 4 threads.

Caveats:

  • Total memory of a Phi coprocessor is 8 GB, so native mode cannot be used for simulations asking for huge memory.
  • Each Phi coprocessor core is a in-order low voltage one with a clock lower respect  to the CPU, so single core performances are not comparable with a classical CPU one

 

Here you'll find some examples (both in Fortran and in C language):